Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures

Increased variability renders nanometer circuits extremely prone to timing errors that threaten system functionality and reliability. To protect circuits from timing errors, designers adopt pessimistic timing margins, which lead to energy inefficiency. This dissertation focuses on addressing the challenges related to energy efficiency and timing errors in a collective fashion. The rate and impact of such errors depend on their manifestation across the layers of the application, microarchitecture and circuit. Accordingly, this thesis investigates cross-layer methods to mitigate, evaluate and model timing errors, exploiting the data-dependent timing behaviour of pipelined designs. In the first part of this thesis, techniques that minimise, detect, and prevent timing errors are proposed. At the circuit-layer, this thesis investigates the root causes of timing errors and proposes a framework that isolates the timing critical paths to a single pipeline stage. At microarchitecture-layer, a dynamic cycle adjustment technique is devised to prevent timing errors in case of excitation of a timing critical path. At application/software-layer, the concept of approximate computing is leveraged to minimise timing errors. In the second part, two accurate timing error modeling and evaluation frameworks are proposed; for the first time the instruction execution history (i.e., type and order of instructions within a pipeline at any instant) is considered. DEFCON, a fully automated framework which customises a genetic algorithm driven by accurate dynamic timing analysis to stochastically search for microarchitecture-aware instructions that trigger timing errors, is presented. ARETE is then derived, a novel framework that enables fully-accurate impact-evaluation of timing errors on applications by combining dynamic binary instrumentation with machine learning-guided dynamic timing analysis.<br/><br/>Finally, the inherent complex dynamic timing behaviour of pipelined architectures is exploited and a low power security primitive for hardware-rooted device authentication is proposed. To achieve this, DTA-PUF, a novel lightweight physical unclonable function, is introduced.

Name dc:type.qualificationname

Doctor of Philosophy

Level dc:type.qualificationlevel

Doctoral Thesis

Grantor dc:publisher.institution

Queen's University Belfast

Year dc:date.issued

2021

Author dc:creator

• Tsiokanos, Ioannis

Advisors dc:contributor.advisor

• Karakonstantis, Georgios
• Woods, Roger
• Nikolopoulos, Dimitrios S.

• Timing errors,
• low-power FPU
• energy efficiency
• reliability
• hardware security
• PUF
• pipelined designs
• dynamic timing analysis
• machine learning
• genetic algorithm

Language dc:language

eng

Identifier

oai:pure.qub.ac.uk/portal:studenttheses/90ed37e4-c2b4-44b1-bf58-418655db9dfb

OAI identifier oai:identifier

oai:pure.qub.ac.uk/portal:studenttheses/90ed37e4-c2b4-44b1-bf58-418655db9dfb