Charged device model electrostatic discharge failures in system on a chip and system in a package designs

Advances in integrated circuit design and packaging techniques have introduced new ESD-susceptible (Electrostatic Discharge) circuit interfaces. This document will introduce these interfaces and the methods that were used to investigate their ESD robustness. Two test chips were designed to aid the analysis. The specialized design choices that allow for distinguishing between multiple failure locations are thoroughly illustrated. The testing plan is detailed and the test chip measurement results are analyzed. The results will compare different ESD protection techniques and illustrate the importance of having ESD protection at these interfaces. The results will also show how some interfaces are inherently more robust than others during a CDM (Charged Device Model) event. Finally, the effects on the intensity of the CDM stress based on single-die or stacked-die packages will be compared.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Olson, Nicholas A.

Contributors dc:contributor

• Rosenbaum, Elyse
• Feng, Milton
• Shanbhag, Naresh R.
• Schutt-Ainé, José E.

• Charged Device Model
• Charged Device Model (CDM)
• Electrostatic Discharge (ESD)
• Electrostatic Discharge
• System on a Chip
• System in a Package

Statement dc:rights

• Copyright 2011 Nicholas A. Olson

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/24101

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/24101