Back to results
University of Illinois at Urbana-Champaign
Test generation and evaluation for bridging faults in CMOS VLSI circuits
Abstract
dc:descriptionAn efficient automatic test pattern generator for I$\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Engineering, Electronics and Electrical
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Lee, Terry Ping-Chung
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- Copyright 1995 Lee, Terry Ping-Chung
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
-
AAI9624412
(UMI)AAI9624412 - OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/23830