{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/23830"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/23830","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Test generation and evaluation for bridging faults in CMOS VLSI circuits","abstract":"An efficient automatic test pattern generator for I$\\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.","abstract_html":"An efficient automatic test pattern generator for I$\\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.","abstract_has_math":true,"creators":["Lee, Terry Ping-Chung"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Engineering, Electronics and Electrical","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T14:28:42Z","date_published":"2011-05-07T14:28:42Z","updated_at":"2026-07-22T22:25:22Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1995 Lee, Terry Ping-Chung"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9624412","(UMI)AAI9624412"],"render_values":[{"text":"AAI9624412","href":null,"code":true},{"text":"(UMI)AAI9624412","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/23830","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Lee, Terry Ping-Chung"]},{"key":"dc:creator","label":"Author","values":["Lee, Terry Ping-Chung"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T14:28:42Z","10000-01-01","1995"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering, Electronics and Electrical"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1995 Lee, Terry Ping-Chung"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9624412","(UMI)AAI9624412","http://hdl.handle.net/2142/23830"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["An efficient automatic test pattern generator for I$\\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.","To accurately evaluate the test sets, fault grading is performed using a switch-level fault simulator and a mixed-mode electrical-level fault simulator. The test sets are compared with those generated by HITEC, a traditional gate-level test generator. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that for I$\\sb{DDQ}$ testing, the GA test sets outperform the HITEC test sets. When the test sets are truncated due to test time constraints, the fault coverages can differ by 10% or more.","In addition to test generation and test evaluation, diagnosis (fault location) is also performed using both test sets. Diagnosis is performed using fault dictionaries constructed during test evaluation. In addition to the traditional full dictionary, two reduced dictionaries are also presented. The results show that the reduced dictionaries offer good size-resolution trade-offs when compared with the full dictionary.","Made available in DSpace on 2011-05-07T14:28:42Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9624412.pdf: 3868439 bytes, checksum: e3485e05d6f08e5ae2c198cfae7dce3e (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:07:08Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:32:16-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Test generation and evaluation for bridging faults in CMOS VLSI circuits"]}]}],"canonical_facts":{"dc:contributor":["Lee, Terry Ping-Chung"],"dc:creator":["Lee, Terry Ping-Chung"],"dc:date":["2011-05-07T14:28:42Z","10000-01-01","1995"],"dc:description":["An efficient automatic test pattern generator for I$\\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.","To accurately evaluate the test sets, fault grading is performed using a switch-level fault simulator and a mixed-mode electrical-level fault simulator. The test sets are compared with those generated by HITEC, a traditional gate-level test generator. Experimental results for ISCAS85 and ISCAS89 benchmark circuits are presented. The results show that for I$\\sb{DDQ}$ testing, the GA test sets outperform the HITEC test sets. When the test sets are truncated due to test time constraints, the fault coverages can differ by 10% or more.","In addition to test generation and test evaluation, diagnosis (fault location) is also performed using both test sets. Diagnosis is performed using fault dictionaries constructed during test evaluation. In addition to the traditional full dictionary, two reduced dictionaries are also presented. The results show that the reduced dictionaries offer good size-resolution trade-offs when compared with the full dictionary.","Made available in DSpace on 2011-05-07T14:28:42Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9624412.pdf: 3868439 bytes, checksum: e3485e05d6f08e5ae2c198cfae7dce3e (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:07:08Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:32:16-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9624412","(UMI)AAI9624412","http://hdl.handle.net/2142/23830"],"dc:language":["eng"],"dc:rights":["Copyright 1995 Lee, Terry Ping-Chung"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Test generation and evaluation for bridging faults in CMOS VLSI circuits"],"dc:type":["text"],"thesis:degree_discipline":["Engineering, Electronics and Electrical"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:22Z"}