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University of Illinois at Urbana-Champaign

Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits

Abstract

dc:description

The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2011

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Sun, Weishi
Contributors dc:contributor
  • Kang, Sung Mo

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • Copyright 1995 Sun, Weishi
Language dc:language
eng

Identifiers

dc:identifier.*
Identifier
AAI9624504
(UMI)AAI9624504
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/23180

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Sun, Weishi. Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits. Dissertation thesis, University of Illinois at Urbana-Champaign, 2011. http://hdl.handle.net/2142/23180