{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/23180"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/23180","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits","abstract":"The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.","abstract_html":"The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.","abstract_has_math":false,"creators":["Sun, Weishi"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Kang, Sung Mo"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T14:04:59Z","date_published":"2011-05-07T14:04:59Z","updated_at":"2026-07-22T22:25:21Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1995 Sun, Weishi"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9624504","(UMI)AAI9624504"],"render_values":[{"text":"AAI9624504","href":null,"code":true},{"text":"(UMI)AAI9624504","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/23180","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, Sung Mo"]},{"key":"dc:creator","label":"Author","values":["Sun, Weishi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T14:04:59Z","10000-01-01","1995"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1995 Sun, Weishi"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9624504","(UMI)AAI9624504","http://hdl.handle.net/2142/23180"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.","As device sizes shrink into the submicron region, pMOS transistor hot-carrier degradation becomes increasingly more important. There has not, however, been a widely accepted model for pMOS transistor hot-carrier degradation unlike that for nMOS transistors. Existing reliability simulations tools are primarily based on transistor level simulation and, therefore, can not handle large circuits efficiently. Using the fast-timing-based reliability simulator, ILLIADS-R, and the empirical model developed based on our experimental results, hot-carrier reliability can be well predicted. ILLIADS-R also serves as an integral part of the hierarchical design-for-reliability system.","A new hot-carrier degradation model is developed for submicron pMOS transistors. Using this model, the pMOS transistor hot-carrier degradation can be predicted based on the total injected charge into the gate oxide region and the initial gate current under normal operating condition. This model is integrated into the fast-timing-based reliability simulation tool, ILLIADS-R. The simulation results demonstrate that ILLIADS-R outperforms the existing reliability simulator BERT in terms of simulation speed with a comparable accuracy. Also studied are the pMOS transistor subthreshold leakage characteristics as a function of hot-carrier stress conditions. It is shown that subthreshold leakage current is a future limit to the pMOS device lifetime.","Made available in DSpace on 2011-05-07T14:04:59Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9624504.pdf: 3129117 bytes, checksum: 95dbb268a59b663e869906d98f09ec31 (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:43Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:51-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits"]}]}],"canonical_facts":{"dc:contributor":["Kang, Sung Mo"],"dc:creator":["Sun, Weishi"],"dc:date":["2011-05-07T14:04:59Z","10000-01-01","1995"],"dc:description":["The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.","As device sizes shrink into the submicron region, pMOS transistor hot-carrier degradation becomes increasingly more important. There has not, however, been a widely accepted model for pMOS transistor hot-carrier degradation unlike that for nMOS transistors. Existing reliability simulations tools are primarily based on transistor level simulation and, therefore, can not handle large circuits efficiently. Using the fast-timing-based reliability simulator, ILLIADS-R, and the empirical model developed based on our experimental results, hot-carrier reliability can be well predicted. ILLIADS-R also serves as an integral part of the hierarchical design-for-reliability system.","A new hot-carrier degradation model is developed for submicron pMOS transistors. Using this model, the pMOS transistor hot-carrier degradation can be predicted based on the total injected charge into the gate oxide region and the initial gate current under normal operating condition. This model is integrated into the fast-timing-based reliability simulation tool, ILLIADS-R. The simulation results demonstrate that ILLIADS-R outperforms the existing reliability simulator BERT in terms of simulation speed with a comparable accuracy. Also studied are the pMOS transistor subthreshold leakage characteristics as a function of hot-carrier stress conditions. It is shown that subthreshold leakage current is a future limit to the pMOS device lifetime.","Made available in DSpace on 2011-05-07T14:04:59Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9624504.pdf: 3129117 bytes, checksum: 95dbb268a59b663e869906d98f09ec31 (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:43Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:51-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9624504","(UMI)AAI9624504","http://hdl.handle.net/2142/23180"],"dc:language":["eng"],"dc:rights":["Copyright 1995 Sun, Weishi"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:21Z"}