Efficient direct-method parallel circuit simulation using multilevel node tearing

The direct-method circuit simulation technique solves the entire system at every iteration and thus avoids the problem of slow convergence or even nonconvergence, which could occur when relaxation-based techniques are applied. However, the parallelism of the direct method is not as obvious as that of the relaxation technique. The parallelism in the LU factorization without tearing has been found to be small and one level node tearing could have a large border size if it is forced to partition the circuit into a fixed number of subcircuits. In this thesis we increase the parallelism by using a multilevel node tearing method which maintains a minimum border size while trying to balance the subcircuit sizes. The problems of how to maximize the speedup by scheduling the subcircuits correctly and by choosing the optimal number of levels of partitioning are also studied. A parallel circuit simulator, iPRIDE, is implemented on an ALLIANT FX/8 computer using these techniques. A speedup of 7.3 using 8 processors has been achieved.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Chang, Mi-Chang

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1989 Chang, Mi-Chang

Language dc:language

eng

Identifier

AAI8916223
(UMI)AAI8916223

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/23126