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University of Illinois at Urbana-Champaign

Automatic layout synthesis for high-performance full custom VLSI chips

Abstract

dc:description

As the technology advances, millions of transistors can be integrated on a small chip area. With the trend, the physical layout synthesis by human designers becomes costly and error prone due to the various design constraints. Therefore, the demands for intelligent tools have been increasing to create physical layouts for custom logic design. We developed an automatic layout synthesis system for high-performance full custom circuits. In this thesis, we introduce our synthesis system in conjunction with related problems and solutions. Most of the problems in physical layout synthesis, namely, leaf cell construction, partitioning, placement, global routing, detailed routing and transistor/gate sizing, are addressed in our synthesis system. All necessary leaf cells are individually synthesized with customized transistor sizes before placement and tuned after detailed routing. We developed various techniques for the leaf cells synthesis to match layout experts, such as transistor folding, transistor ordering, contact placement and transistor sizing. In partitioning and placement, we concentrated our effort on data path circuits, which is one of the currently popular topics. For detailed routing, a triple-metal-layer over-the-cell router has been developed for a popular platform. Our synthesis system iteratively improves the layout until given requirements are satisfied. We tested our system with various benchmark circuits to measure the performance. Also, a whole chip layout, including bonding pads for DSP circuits, has been synthesized with a hierarchical design scheme.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Computer Science
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2011

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Kim, Jaewon
Contributors dc:contributor
  • Kang, Sung Mo

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • Copyright 1995 Kim, Jaewon
Language dc:language
eng

Identifiers

dc:identifier.*
Identifier
AAI9624390
(UMI)AAI9624390
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/22950

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Kim, Jaewon. Automatic layout synthesis for high-performance full custom VLSI chips. Dissertation thesis, University of Illinois at Urbana-Champaign, 2011. http://hdl.handle.net/2142/22950