Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 8 of 8 for “"Gate Sizing"”.
-
Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization
<p>The modeling of an individual gate and the optimization of circuit performance has long been a critical issue in the VLSI industry. In this work, we first study of the gate sizing problem for today's industrial designs, and explore the contributions and limitations of all the existing …
-
Techniques for VLSI Circuit Optimization Considering Process Variations
… for circuit optimization methods such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant …
-
Utilitarian Approaches for Multi-Metric Optimization in VLSI Circuit Design and Spatial Clustering
… research, several utilitarian methods are investigated for variation aware multi-metric optimization in VLSI circuit design and spatial pattern clustering. A novel algorithm based on the concepts of utility theory and risk minimization is developed for variation aware multi-metric optimization of …
-
Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… or other structures). In this work, we investigate optimized micro-channel configurations that address the aforementioned considerations. We develop three micro-channel structures (hotspot optimized cooling configuration, bended micro-channel and hybrid cooling network) that can provide …
-
Architecture and CAD techniques for optimizing FPGAs and reliability of integrated circuits.
… propose CAD and architecture techniques to mitigate the impact of process variations in FPGAs. We present a variation-aware router that optimizes statistical timing criticality. We then propose a modification to the clock network to deliver programmable skews to different flip-flops. Finally, we …
-
Automatic layout synthesis for high-performance full custom VLSI chips
… global routing, detailed routing and transistor/gate sizing, are addressed in our synthesis system. All necessary leaf cells are individually synthesized with customized transistor sizes before placement and tuned after detailed routing. We developed various techniques for the leaf cells …
-
Performance variations due to layout-dependent stress in VLSI circuits
… The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performance induced by TSV stress. Finally, layout guidelines are presented that optimize circuit …
-
Test and diagnosis of resistive bridges in multi-Vdd designs
… designs. Taking this issue into account, another gate sizing (GS) based DFT technique is proposed. It targets bridges that require multi-Vdd test and increases the drive strength of gates driving such bridges. The number of test Vdd settings are reduced minimizing test cost. Experimental results …