Task scheduling in high-level synthesis

High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses scheduling and allocation in high-level synthesis. Specifically, we study the problem of register allocation in the presence of conditional blocks, such as if and case blocks and loops in the data flow graph. A conditional block in a data flow graph introduces the opportunity of conditional resource sharing among the values of variables in the mutually exclusive conditional branches of the conditional block. We also consider the problem of scheduling, allocation and memory module partition to reduce power consumption. We offer an integrated high-level synthesis sytem SAMP to the solution of the scheduling, allocation (memory units and functional units), functional module selection and partitioning for low power design. SAMP exploits two possibilities of reducing total power consumption. First, it provides a general library in which there are functional modules that perform the same computation but have different speeds and power consumption. Often, low power functional modules are slower while high power functional modules are faster. Second it allows dynamic localized shutdown of functional modules by clock gating to reduce power consumption. Since CMOS circuits consume only a negligible amount of power when they are not switching, inhibiting unnecessary circuit switching activities in functional modules and clock signals will lead to a reduction of power consumption.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Park, Chaeryung

Contributors dc:contributor

• Liu, C.L.

• Computer Science

Statement dc:rights

• Copyright 1996 Park, Chaeryung

Language dc:language

eng

Identifier

AAI9625178
(UMI)AAI9625178

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22891