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Showing 1 to 5 of 5 for “"module selection"”.

  1. Throughput Constrained and Area Optimized Dataflow Synthesis for FPGAs

    … meets the throughput requirement. The second is module selection, which decides the most appropriate circuit module for each operation. The third is resource sharing, which reuses a circuit module by sharing it between multiple operations. This work shows that combining module selection and …

    byu Repository record for Throughput Constrained and Area Optimized Dataflow Synthesis for FPGAs (opens in a new tab)

  2. Transforming Medical Image Segmentation with Enhanced U-Net Architectures and Adaptive Transfer Learning

    … related to architecture, transfer learning, module selection and fine-tuning, and evaluation strategies. Finally, by comparing our models with state-of-the-art approaches on benchmark datasets, we demonstrate their significant potential to contribute to medical image segmentation.

    umkc Repository record for Transforming Medical Image Segmentation with Enhanced U-Net Architectures and Adaptive Transfer Learning (opens in a new tab)

  3. Design and Optimization of a High Power Density Silicon Carbide Traction Inverter

    … needs in the 150-kW range. Following topology selection, the smallest silicon carbide power module that met the electrical requirements of the system was found through experimental testing and simulation. After a power module selection was finalized, a DC link capacitor bank was designed by …

    arkansas Repository record for Design and Optimization of a High Power Density Silicon Carbide Traction Inverter (opens in a new tab)

  4. Task scheduling in high-level synthesis

    … the problem of scheduling, allocation and memory module partition to reduce power consumption. We offer an integrated high-level synthesis sytem SAMP to the solution of the scheduling, allocation (memory units and functional units), functional module selection and partitioning for low power …

    uiuc Repository record for Task scheduling in high-level synthesis (opens in a new tab)

  5. High-Level Resource Binding and Allocation for Power and Performance Optimization

    … variation-aware high-level synthesis binding and module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing-driven …

    uiuc Repository record for High-Level Resource Binding and Allocation for Power and Performance Optimization (opens in a new tab)