BETA: Behavioral Testability Analyzer and its applications to high-level test generation and synthesis for testability

In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach called Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Chen, Chung-Hsing

Contributors dc:contributor

• Saab, Daniel G.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1993 Chen, Chung-Hsing

Language dc:language

eng

Identifier

AAI9314851
(UMI)AAI9314851

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22440