Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 55 for “"testability"”.
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Exposing testability in GUI objects
Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
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Testability of linear-invariant properties
… that can lead to a unified analysis of the testability of all linear-invariant properties, drawing on techniques from additive combinatorics and from graph theory. We also show the first nontrivial lowerbound for the query complexity of a natural testable linear-invariant property.
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BETA: Behavioral Testability Analyzer and its applications to high-level test generation and synthesis for testability
In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test …
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The testability of regular logic structures
… and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex …
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Measuring Evolutionary Testability of Real-Time Software
… attempt to capture these aspects of evolutionary testability. The validation of the measures through a technique which was introduced by Shepperd and Ince, identifies three core measures which can be used to predict evolutionary testability for dynamic timing analysis. These are measures for …
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A Design Methodology for Physical Design for Testability
Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in …
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Issues in Design for Testability and Self-Test
This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.
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Design and synthesis for testability using architectural descriptions
Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:49:51Z Item is restricted indefinitely.
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Design for pre-bond testability in 3D integrated circuits
… and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.
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High-Level Testability Analysis and Enhancement for Digital Systems
The proposed high-level testability analysis technique can also be applied toward paxtial-scan selection for the gate-level design-for-testability approach. A testability grading technique is developed to quantitatively represent the testability of the design. During testability evaluation, a …
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Enhancing testability of VLSI circuits using partial reset techniques
… must be more testable. Several design for testability (DFT) schemes which trade off various design parameters have been proposed towards that end. The primary focus of this research is a technique called partial reset (PR). Rather than allowing all memory elements in a sequential circuit to …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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Integrated Enhancement of Testability and Diagnosability for Digital Circuits
… point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also …
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Timing verification and synthesis of circuits for delay fault testability
… and synthesis of circuits for robust delay fault testability. The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the …
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Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips
… the logic-circuit model, we present a design-for-testability technique that can achieve 100\% fault coverage.</p><p>Finally, this thesis presents a technique for the automated diagnosis of leakage and blockage defects. The proposed method targets the identification of defect types and their …
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The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Embargo set by: Seth Robbins for item 69555 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
… methods for inserting test-points to enhance the testability of a circuit in such a way as to allow even further reduction in the number of seeds.
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Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
… Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL). </p>
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