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University of Illinois at Urbana-Champaign
Logic and layout optimizaton for sequential circuits
Abstract
dc:descriptionComputer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further broken into a few optimization problems. In this thesis we study several such problems in logic and layout synthesis.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Pan, Peichen
- Contributors dc:contributor
-
- Liu, C.L.
Subjects
dc:subject × 3Rights
dc:rights- Statement dc:rights
-
- Copyright 1995 Pan, Peichen
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
-
AAI9624456
(UMI)AAI9624456 - OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/22435