Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 37 for “"Sequential Circuits"”.
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Synthesis heuristics for large asynchronous sequential circuits
… well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to "large" circuits with, for example, three or more input variables and twenty or more …
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Automatic Test Generation Techniques for Sequential Circuits
… test generation approach is proposed for sequential circuits. A simple GA, which interacts with an efficient diagnostic fault simulator, is proposed to target groups of undistinguished fault pairs iteratively. Efficient data structures are used and heuristics are proposed to seed the …
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Logic and layout optimizaton for sequential circuits
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further broken into a few optimization problems. In this thesis we study several such problems in logic and layout synthesis.
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The Design of Multiple-Valued Asynchronous Sequential Circuits
Made available in DSpace on 2014-12-10T19:07:26Z (GMT). No. of bitstreams: 1 7511697.pdf: 3869510 bytes, checksum: 12443605636cd14bfec43f671bc6f73e (MD5) Previous issue date: 1974
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On improving parallel pattern single fault propagation for synchronous sequential circuits
… efficient for fault simulation of combinational circuits. Recently, PPSFP has been extended to synchronous sequential circuits [1]. The fault simulator called PARIS is the unique sequential circuit fault simulator based on PPSFP. In this thesis, four new heuristics are proposed to enhance the …
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On improving the performance of parallel fault simulation for synchronous sequential circuits
… of parallel fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of faults simulated in parallel, the …
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Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits
… called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults is simulated in parallel. Several new heuristics are employed in HOPE to accelerate the parallel fault simulation. The …
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Design Automation Flow for Voltage Adaptive Light Vth Hopping for Leakage Minimization in Sequential Circuits
… in increased leakage power consumption in VLSI circuits. Even though there are several power consumption reduction techniques in the industry today, the increasing leakage power consumption in the deep submicron CMOS technologies has manifested the need for more aggressive control mechanisms. …
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Optimal state assignment of sequential circuits using a genetic local search with flexible cost functions
In this dissertation, we solve the finite state machine (FSM) state assignment problem using an implementation of a genetic local search algorithm (GLS) that selectively targets design goals with the use of flexible cost functions. Our GLS quickly converges toward a globally optimal state encoding, …
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An asynchronous circuit design language system
… for specifying the behavior of asynchronous sequential circuits. The system consists of a special purpose Asynchronous Circuit Design Language (ACDL), a translator and a flow table generation algorithm. The language includes many special features which permit quick and precise specification …
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Diagnostic test set evaluation and enhancement
… problem in the design and manufacturing of VLSI circuits. This thesis contributes to two important diagnosis topics, namely diagnostic fault simulation and diagnostic test pattern generation. First, a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and …
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Knowledge-based testing of VLSI circuits
… addresses the problem of testing complex VLSI circuits. Traditional test generation used either low level gate descriptions or low level heuristics such as controllability and observability. In this thesis we have introduced a knowledge based approach to testing, which is based on (i) a …
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Symbolic methods for testing digital circuits
… of testing both combinational and synchronous sequential digital circuits at gate level. <br>Both major topics, fault simulation and automated test pattern generation (ATPG), have been examined, among others, like build-in self-test, computing reset sequences for a sequential circuit, …
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Functional models for MOS VLSI circuits
… Computer-Aided-Design applications for VLSI circuits is considered. A method for the automatic generation of functional models for switch- and gate-level circuits is presented. In addition, the use of these models is considered in four CAD applications: switch-level simulation, verification …
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Simulation- and Deduction-Based Techniques for Fault Diagnosis
… for the diagnosis of bridging faults in sequential circuits is presented. During diagnosis, the failing outputs from the test are used to adaptively determine the behavior of the bridge at each time-frame. Selective faulty state information is stored by performing accurate bridging fault …
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The E-algorithm: an automatic test generation algorithm for hardware description languages
… test generation techniques for digital circuits have been rendered inadequate by the increasing levels of integration achieved by VLSI technology. This thesis presents a test generation algorithm, the E-algorithm, that generates tests for circuits described using the VHDL Hardware …
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Compressed and dynamic fault dictionaries for fault isolation
… the diagnostic capabilities of a test set. Sequential compression makes no approximations for sequential circuits and thus loses no resolution; however, it costs more than List Splitting, requiring two fault simulations.
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Static Learning for Problems in VLSI Test and Verification
… verification: (1) Efficient identification of sequentially untestable stuck-at faults, and (2) Equivalence checking of sequential circuits. Additionally, for the dissertation, we define a new concept called multi-cycle path delay faults (M-pdf) for latch based designs with multiple clock …
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Experimental results on aliasing errors in circular BIST design
… to synthesize circular BIST hardware on general sequential circuits has been developed. A parallel fault simulator has been developed to detect aliasing errors in circular BIST design. Experimental results on aliasing probability in circular BIST design are reported for twenty-three sequential …
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