On improving parallel pattern single fault propagation for synchronous sequential circuits

The parallel pattern single fault propagation (PPSFP) method is known to be the most efficient for fault simulation of combinational circuits. Recently, PPSFP has been extended to synchronous sequential circuits [1]. The fault simulator called PARIS is the unique sequential circuit fault simulator based on PPSFP. In this thesis, four new heuristics are proposed to enhance the speed of PARIS. The four heuristics are: 1. Immediate fault dropping after every iteration, 2. Filler bit simulation at the first packet 3. Look-ahead of initial states, and 4. Single bit correction for flip-flop evaluation. The four heuristics have been implemented separately, and the performance of the heuristics were measured. According to our results, the four heuristics improve the speed of most benchmark circuits. The four heuristics are integrated into a fault simulator, which we call VISION. The speed of VISION is, on an average, 1.3 times faster than PARIS for the benchmark circuits.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1994

Author dc:creator

• Nair, Rajesh

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-06302009-040508

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43511