Functional verification and timing analysis of large digital emitter-coupled logic circuits including voltage regulators

This thesis describes the algorithms implemented in a new digital emitter-coupled logic (ECL) simulation tool called iECLSIM (Illinois ECL SIMulator). From a transistor-level description, we first partition the circuit into blocks at base nodes and voltage source nodes to exploit latency in time and space. Blocks are identified as either voltage source blocks or switching blocks automatically. The voltage source blocks are simulated at dc only to accurately calculate reference voltages.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Brauer, Elizabeth Jewel

Contributors dc:contributor

• Kang, Sung Mo

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1994 Brauer, Elizabeth Jewel

Language dc:language

eng

Identifier

AAI9416339
(UMI)AAI9416339

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22100