Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability

In this thesis, an integrated simulation approach is presented for estimating the hot-carrier induced degradation of MOSFET device characteristics and circuit performance. The proposed simulation tool provides information on (i) the evolution of device and circuit performance degradation during long-term dynamic operation, (ii) the amount of hot-carrier induced damage in each transistor after a specified operation period, and (iii) the performance characteristics of the damaged circuit. This information can be used both for understanding the circuit-level dynamics of the degradation mechanisms and as a design aid, for improving the long-term circuit reliability through design modifications.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Leblebici, Yusuf

Contributors dc:contributor

• Kang, Sung Mo

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1991 Leblebici, Yusuf

Language dc:language

eng

Identifier

AAI9124450
(UMI)AAI9124450

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21963