Modeling simulation and design guidelines for EOS/ESD protection circuits in CMOS technologies

Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Ramaswamy, Sridhar

Contributors dc:contributor

• Kang, Sung Mo

• Engineering, Electronics and Electrical
• Physics, Electricity and Magnetism
• Physics, Condensed Matter

Statement dc:rights

• Copyright 1996 Ramaswamy, Sridhar

Language dc:language

eng

Identifier

9780591200423
AAI9712413
(UMI)AAI9712413

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21863