{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21863"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21863","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling simulation and design guidelines for EOS/ESD protection circuits in CMOS technologies","abstract":"Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.","abstract_html":"Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.","abstract_has_math":false,"creators":["Ramaswamy, Sridhar"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Kang, Sung Mo"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:21:29Z","date_published":"2011-05-07T13:21:29Z","updated_at":"2026-07-22T22:25:18Z","subjects":["Engineering, Electronics and Electrical","Physics, Electricity and Magnetism","Physics, Condensed Matter"],"languages":["eng"],"rights":["Copyright 1996 Ramaswamy, Sridhar"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["9780591200423","AAI9712413","(UMI)AAI9712413"],"render_values":[{"text":"9780591200423","href":null,"code":true},{"text":"AAI9712413","href":null,"code":true},{"text":"(UMI)AAI9712413","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21863","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, Sung Mo"]},{"key":"dc:creator","label":"Author","values":["Ramaswamy, Sridhar"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:21:29Z","10000-01-01","1996"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Physics, Electricity and Magnetism","Physics, Condensed Matter"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1996 Ramaswamy, Sridhar"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["9780591200423","AAI9712413","(UMI)AAI9712413","http://hdl.handle.net/2142/21863"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.","In this thesis, we have provided a review of various on-chip protection circuits commonly used in advanced CMOS ICs. We propose that current profiles should be used for EOS qualification. We show that current profiles, along with failure analyses, can be used to develop useful design guidelines for EOS/ESD protection circuit layout. We investigate the effect of chip capacitance on the EOS/ESD performance of protection circuits and provide guidelines for device design. Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications. We provide practical guidelines for designing protection devices in this technology.","Recent advances in processing technology and very-large-scale integration (VLSI) scaling has increased the demand for more effective protection circuits. So far, no significant modeling programs were available to analyze and design these circuits. We have developed models which describe the high current behavior in MOSFETs, diffusion resistors, reverse-biased diodes and bipolar transistors. These models have been included in the circuit-level electrothermal simulator, iETSIM.","It has been shown that at second breakdown, the protection device suffers permanent damage. By modeling the device behavior up to the onset of second breakdown, we can determine the operation limit of the protection element. We have developed electrothermal models to describe the onset of second breakdown in the protection devices. In semiconductor junctions that are reverse-biased by an EOS event, second breakdown is shown to occur when the thermal generation current becomes high enough to sustain the stress and the generation of carriers due to impact ionization decreases. Electrothermal models for MOSFETs, diffusion resistors, diodes and bipolar transistors have been included in iETSIM, which can predict the EOS robustness of these protection elements.","Made available in DSpace on 2011-05-07T13:21:29Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9712413.pdf: 5476587 bytes, checksum: 3b48572aa0b92d71b2bf2294494e30e7 (MD5) Previous issue date: 1996","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:53:42Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:24:52-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Modeling simulation and design guidelines for EOS/ESD protection circuits in CMOS technologies"]}]}],"canonical_facts":{"dc:contributor":["Kang, Sung Mo"],"dc:creator":["Ramaswamy, Sridhar"],"dc:date":["2011-05-07T13:21:29Z","10000-01-01","1996"],"dc:description":["Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.","In this thesis, we have provided a review of various on-chip protection circuits commonly used in advanced CMOS ICs. We propose that current profiles should be used for EOS qualification. We show that current profiles, along with failure analyses, can be used to develop useful design guidelines for EOS/ESD protection circuit layout. We investigate the effect of chip capacitance on the EOS/ESD performance of protection circuits and provide guidelines for device design. Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications. We provide practical guidelines for designing protection devices in this technology.","Recent advances in processing technology and very-large-scale integration (VLSI) scaling has increased the demand for more effective protection circuits. So far, no significant modeling programs were available to analyze and design these circuits. We have developed models which describe the high current behavior in MOSFETs, diffusion resistors, reverse-biased diodes and bipolar transistors. These models have been included in the circuit-level electrothermal simulator, iETSIM.","It has been shown that at second breakdown, the protection device suffers permanent damage. By modeling the device behavior up to the onset of second breakdown, we can determine the operation limit of the protection element. We have developed electrothermal models to describe the onset of second breakdown in the protection devices. In semiconductor junctions that are reverse-biased by an EOS event, second breakdown is shown to occur when the thermal generation current becomes high enough to sustain the stress and the generation of carriers due to impact ionization decreases. Electrothermal models for MOSFETs, diffusion resistors, diodes and bipolar transistors have been included in iETSIM, which can predict the EOS robustness of these protection elements.","Made available in DSpace on 2011-05-07T13:21:29Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9712413.pdf: 5476587 bytes, checksum: 3b48572aa0b92d71b2bf2294494e30e7 (MD5) Previous issue date: 1996","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:53:42Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:24:52-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["9780591200423","AAI9712413","(UMI)AAI9712413","http://hdl.handle.net/2142/21863"],"dc:language":["eng"],"dc:rights":["Copyright 1996 Ramaswamy, Sridhar"],"dc:subject":["Engineering, Electronics and Electrical","Physics, Electricity and Magnetism","Physics, Condensed Matter"],"dc:title":["Modeling simulation and design guidelines for EOS/ESD protection circuits in CMOS technologies"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:18Z"}