Incremental circuit simulation and timing analysis techniques

Most integrated circuit designs must be iterated in the design cycle for tens or even hundreds times to correct all of the violations and/or to optimize the performance. At the latter portion of the design cycles, only small changes are made and most of the circuit characteristics remain unchanged. However, normal CAD tools would still take the same amount of time to re-examine the slightly modified design. Incremental CAD algorithms are based on the idea that it usually takes much less time to update invalid information than to do a complete analysis if the worst case implication of a design change can be identified efficiently. In our research, we realize that if an algorithm can be carefully decomposed into several independent phases, then some phases may be either totally skipped or easily updated to reduce the execution time and to give the designers faster feedback. In addition, for some applications, the results generated in the previous analysis can provide a good initial solution for the new run.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Ju, Yun-Cheng

Contributors dc:contributor

• Saleh, Resve A.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1992 Ju, Yun-Cheng

Language dc:language

eng

Identifier

AAI9236494
(UMI)AAI9236494

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21711