Timing verification and synthesis of circuits for delay fault testability

This thesis concerns the problem of timing verification and synthesis of circuits for robust delay fault testability. The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are considered.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Roy, Kaushik

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1990 Roy, Kaushik

Language dc:language

eng

Identifier

AAI9114393
(UMI)AAI9114393

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21540