Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 41 for “"Register Transfer Level"”.
-
High Quality Test Generation at the Register Transfer Level
… must be approached from several different design levels. In particular, exploiting the Register Transfer Level for test generation allows for the use of relational information unavailable at the structural level. This dissertation demonstrates several novel methods for generating tests applicable …
-
Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration
… process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can …
-
Power Macro-modelling for IP-based Digital Systems at Register Transfer Level : Macromodelado del consumo de sistemas digitales basados en IPs descritos a nivel de transferencia de registros
… However, there are still few architecture level power estimation tools that can be used over technology generations and is capable of modeling arbitrary circuits. A key challenge in the design of low power systems is the fast and accurate estimation of power dissipation. Power is a strongly …
-
A system for microarchitecture and logic optimization
… and logic synthesis tools. This thesis spans two levels of the design process by examining optimization at both the register-transfer level and at the logic level. More specifically, this thesis addresses the following two problems: (1) performing logic synthesis for custom layout rather than the …
-
Static Analysis to improve RTL Verification
… the effort of testing and verification at the register transfer level. Studying a design at register transfer level gives exposure to the relational information for the design which is inaccessible at the structural level. In this thesis, we present a way to generate a Data Dependency Graph and …
-
Timing verification and synthesis of circuits for delay fault testability
… The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are …
-
Constraint Driven Behavioral Synthesis
… set of imposed constraints are used to design a register-transfer level implementation of the desired machine. Several runs of the system are presented and annotated including a design of a TMS320 DSP chip from a behavioral description of its operation.
-
Enhancing quality of assertion generation: methods for automatic assertion generation and evaluation
… for automatically generating and evaluating register transfer level (RTL) assertions. We detail the GoldMine methodology and each of its data mining algorithms. We introduce the Best-Gain Decision Forest algorithm to mine concise RTL assertions. We develop an assertion ranking methodology. We …
-
Algorithms for Logic Design Automation (Rtcad, Synthesis)
… integrated circuit which corresponds to a high level behavioral description of a logic circuit. This thesis describes a collection of algorithms that transform a graph data structure derived from a behavior description into a logic design at the register transfer level.
-
Hardware Trojan Detection via Golden Reference Library Matching
… This methodology analyzes a soft IP at the register-transfer level to discover malicious inclusions. An extension of this methodology is presented that expands the list of signal functionalities, termed assets, in addition to introducing a methodology for matching soft IPs to a functionality …
-
Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification
… The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software ("C" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, …
-
Goldmine: An integration of data mining and static analysis for automatic generation of hardware assertions
… of data mining and static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for ""candidate assertions"" that are likely to be invariants. We present both a decision …
-
Timing distribution in VHDL behavioral models
… device are made available. Also, due to the Register Transfer Level (RTL) of abstraction, which is represented by a process model graph, there is close correspondence with the actual device being modeled. Thus a better insight into the timing problems is provided and synthesis is possible …
-
Guiding RTL Test Generation Using Relevant Potential Invariants
… test vectors for design validation at the Register Transfer Level (RTL). Providing useful guidance to the test generator for such techniques is critical. In our approach, we provide guidance by exploiting potential invariants in the design. These potential invariants are obtained using …
-
High-Level CSP Model Compiler for FPGAs
… time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also …
-
A framework for synthesis from VHDL
… of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. …
-
Guarded atomic actions and refinement in a system-on-chip development flow: bridging the specification gap with Event-B
… and verification flows, languages and tools. The Register Transfer Level (RTL)description, which forms the input for synchronous, logic synthesis-driven design is at too low a level of abstraction for efficient architectural exploration and re-use. The existing methods for taking a high-level …
-
RTL Functional Test Generation Using Factored Concolic Execution
… test generation framework that uses it for high-level functional test generation. The test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple (factored) explorations. We begin by transforming the Register Transfer Level (RTL) …
-
Coverage analysis for assertions and emulation based verification
… by the test suite code coverage reported by Register Transfer Level (RTL) simulators and the other by assertion correctness in the context of formal verification. We present efficient algorithms to compute coverage with respect to the proposed metrics by analyzing the Control Flow Graph (CFG) …
Page 1 of 3