Parallel algorithms for standard cell placement using simulated annealing

As modern VLSI designs have become larger and more complicated, the computational requirements for design automation tools have also increased. As a result, the parallelization of these tools is of great importance. One of the more computationally intensive parts of the entire VLSI design process is the placement process. Simulated-annealing-based approaches have been the most popular and effective methods for cell placement. In this thesis, parallelization approaches to simulated-annealing-based standard cell placement are presented.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Chandy, John A.

Contributors dc:contributor

• Banerjee, Prithviraj

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1996 Chandy, John Attupurathu

Language dc:language

eng

Identifier

9780591197570
AAI9712216
(UMI)AAI9712216

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21523