Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 53 for “"VLSI Design"”.
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Temperature -Aware VLSI Design and Analysis
… effective framework for temperature-sensitive VLSI design and analysis. This work attempts to provide a comprehensive temperature- and reliability-conscious design solution for dealing with emerging thermal and reliability issues.
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VLSI design for freshmen and sophomores
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
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An integrated simulation for VLSI design environment
Call number: LD2668 .R4 EECE 1989 C53
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Asynchrobatic logic for low-power VLSI design
… Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be used to describe …
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Shape Approximation of Printed Images in VLSI Design
Despite application of optical proximity correction (OPC) and resolution enhancement techniques (RET) to improve printing, limitations in lithography and manufacturing processes still lead to undesirable irregularities in printed images on wafer. These post-lithographic distorted shapes are of …
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Full Custom VLSI Design of On-Line Stability Checkers
… the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI …
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A Convex Programming Approach to Problems in VLSI Design
Two problems in VLSI CAD, namely, those of transistor sizing and design centering, are dealt with in this thesis.
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Parallel algorithms for placement and routing in VLSI design
… quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Past research has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks …
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Application of a silicon complier to VLSI design of digital pipelined multipliers
… of employing the MacPitts silicon compiler to design an 8-bit pipelined digital multiplier is presented, and the resulting design is evaluated. The process of installing and debugging the MacPitts compiler and the Caesar VLSI graphics editor on the VAX-11/780 computing facilities at NPS is …
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Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
… we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of …
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Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System
… makes an FPGA solution slower than an ASIC design. Bit-oriented computational units make them unnecessarily inefficient for implementing tasks that are generally word-oriented. And finally, in large volumes, FPGAs tend to be more expensive per unit due to their lower transistor density. To …
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Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor
This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic …
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Performance-driven placement and routing algorithms
… power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews …
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Parallel algorithms for standard cell placement using simulated annealing
As modern VLSI designs have become larger and more complicated, the computational requirements for design automation tools have also increased. As a result, the parallelization of these tools is of great importance. One of the more computationally intensive parts of the entire VLSI design process …
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Complete VLSI implementation of improved low complexity chase Reed-Solomon decoders
This thesis presents a complete VLSI design of improved low complexity chase (LCC) decoders for Reed-Solomon (RS) codes. This is the first attempt in published research that implements LCC decoders at the circuit level. Based on the joint algorithm research with University of Hawaii, we propose …
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Algorithms for circuit layout compaction of building blocks
… layouts. With the ever increasing complexity of VLSI circuitry, the building block approach becomes very important for custom VLSI design. A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's. The layout area is reduced …
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Logic optimization of MOS networks
… complexity. There is thus an increasing need for designers to rely on the assistance of computer-aided design tools to provide a fast design turnaround and reduce design errors. Logic design (or logic synthesis) is one major step in the ASIC VLSI design cycle in which automation is playing an …
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Design and implementation of three-dimensional logic structures
In this thesis, a computer-aided-design (CAD) system is developed that assists in the design of novel three-dimensional integrated circuits. The software tools allow for the specification of a multilayer transistor circuit by means that are readily accessible to those familiar with two-dimensional …
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Allocating decoupling capacitors to reduce simultaneous switching noise on chips
… of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding …
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Circuits for high-performance low-power VLSI logic
… as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL …
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