Application of a silicon complier to VLSI design of digital pipelined multipliers

The concept and application of silicon compilers is described. The process of employing the MacPitts silicon compiler to design an 8-bit pipelined digital multiplier is presented, and the resulting design is evaluated. The process of installing and debugging the MacPitts compiler and the Caesar VLSI graphics editor on the VAX-11/780 computing facilities at NPS is documented in appendices.

Department dc:contributor.department

Department of Electrical and Computer Engineering

Year dc:date.issued

1984

Author dc:creator

• Carlson, Dennis J.

Advisor dc:contributor.advisor

• Kirk, Donald E.

Statement dc:rights

• This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.

Language dc:language.iso

en_US

Handle dc:identifier.uri

https://hdl.handle.net/10945/19164

OAI identifier oai:identifier

oai:calhoun.nps.edu:10945/19164