Multiprocessor communications: Design and technology

The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic modeling and implementational constraints. In this dissertation, we examine these issues and present new perspectives of various aspects of network design. We first concentrate on the problems that arise from synchronization accesses. In these situations, hot-spots are created, and intense contention results in long delays for these accesses. We evaluate hardware and software enhancements for reducing the latency of hot-spot traffic. Our results indicate that a single-stage shuffle-exchange network with combining hardware is an attractive option, in terms of improved performance at reasonable cost. The second part of the dissertation focuses on the effect of packaging constraints on network performance. Such constraints have important impacts on system architecture, and must be incorporated into network analysis. We focus on architectural clustering as a promising approach to utilize resources efficiently and circumvent implementational difficulties. We find that clustering allows the construction of shared, high bandwidth channels, which are more efficient than dedicated, low bandwidth channels. However, the relative performance of the networks we studied is dependent on system configuration, message granularity and the packaging constraint chosen to be critical. Based on these factors, we can determine the best network for a given system environment.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Hsu, Tsun-yuk

Contributors dc:contributor

• Yew, Pen-Chung

• Computer Science

Statement dc:rights

• Copyright 1992 Hsu, Tsun-yuk

Language dc:language

eng

Identifier

AAI9305558
(UMI)AAI9305558

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21446