{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21446"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21446","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Multiprocessor communications: Design and technology","abstract":"The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic modeling and implementational constraints. In this dissertation, we examine these issues and present new perspectives of various aspects of network design. We first concentrate on the problems that arise from synchronization accesses. In these situations, hot-spots are created, and intense contention results in long delays for these accesses. We evaluate hardware and software enhancements for reducing the latency of hot-spot traffic. Our results indicate that a single-stage shuffle-exchange network with combining hardware is an attractive option, in terms of improved performance at reasonable cost. The second part of the dissertation focuses on the effect of packaging constraints on network performance. Such constraints have important impacts on system architecture, and must be incorporated into network analysis. We focus on architectural clustering as a promising approach to utilize resources efficiently and circumvent implementational difficulties. We find that clustering allows the construction of shared, high bandwidth channels, which are more efficient than dedicated, low bandwidth channels. However, the relative performance of the networks we studied is dependent on system configuration, message granularity and the packaging constraint chosen to be critical. Based on these factors, we can determine the best network for a given system environment.","abstract_html":"The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic modeling and implementational constraints. In this dissertation, we examine these issues and present new perspectives of various aspects of network design. We first concentrate on the problems that arise from synchronization accesses. In these situations, hot-spots are created, and intense contention results in long delays for these accesses. We evaluate hardware and software enhancements for reducing the latency of hot-spot traffic. Our results indicate that a single-stage shuffle-exchange network with combining hardware is an attractive option, in terms of improved performance at reasonable cost. The second part of the dissertation focuses on the effect of packaging constraints on network performance. Such constraints have important impacts on system architecture, and must be incorporated into network analysis. We focus on architectural clustering as a promising approach to utilize resources efficiently and circumvent implementational difficulties. We find that clustering allows the construction of shared, high bandwidth channels, which are more efficient than dedicated, low bandwidth channels. However, the relative performance of the networks we studied is dependent on system configuration, message granularity and the packaging constraint chosen to be critical. Based on these factors, we can determine the best network for a given system environment.","abstract_has_math":false,"creators":["Hsu, Tsun-yuk"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Yew, Pen-Chung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:08:53Z","date_published":"2011-05-07T13:08:53Z","updated_at":"2026-07-22T22:25:18Z","subjects":["Computer Science"],"languages":["eng"],"rights":["Copyright 1992 Hsu, Tsun-yuk"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305558","(UMI)AAI9305558"],"render_values":[{"text":"AAI9305558","href":null,"code":true},{"text":"(UMI)AAI9305558","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21446","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Yew, Pen-Chung"]},{"key":"dc:creator","label":"Author","values":["Hsu, Tsun-yuk"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:08:53Z","10000-01-01","1992"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1992 Hsu, Tsun-yuk"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305558","(UMI)AAI9305558","http://hdl.handle.net/2142/21446"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic modeling and implementational constraints. In this dissertation, we examine these issues and present new perspectives of various aspects of network design. We first concentrate on the problems that arise from synchronization accesses. In these situations, hot-spots are created, and intense contention results in long delays for these accesses. We evaluate hardware and software enhancements for reducing the latency of hot-spot traffic. Our results indicate that a single-stage shuffle-exchange network with combining hardware is an attractive option, in terms of improved performance at reasonable cost. The second part of the dissertation focuses on the effect of packaging constraints on network performance. Such constraints have important impacts on system architecture, and must be incorporated into network analysis. We focus on architectural clustering as a promising approach to utilize resources efficiently and circumvent implementational difficulties. We find that clustering allows the construction of shared, high bandwidth channels, which are more efficient than dedicated, low bandwidth channels. However, the relative performance of the networks we studied is dependent on system configuration, message granularity and the packaging constraint chosen to be critical. Based on these factors, we can determine the best network for a given system environment.","Made available in DSpace on 2011-05-07T13:08:53Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305558.pdf: 6739938 bytes, checksum: b02b26a20a42b8b40995127efc80d47a (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:50:50Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:23:16-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Multiprocessor communications: Design and technology"]}]}],"canonical_facts":{"dc:contributor":["Yew, Pen-Chung"],"dc:creator":["Hsu, Tsun-yuk"],"dc:date":["2011-05-07T13:08:53Z","10000-01-01","1992"],"dc:description":["The performance evaluation of multiprocessor interconnects cannot be divorced from issues of traffic modeling and implementational constraints. In this dissertation, we examine these issues and present new perspectives of various aspects of network design. We first concentrate on the problems that arise from synchronization accesses. In these situations, hot-spots are created, and intense contention results in long delays for these accesses. We evaluate hardware and software enhancements for reducing the latency of hot-spot traffic. Our results indicate that a single-stage shuffle-exchange network with combining hardware is an attractive option, in terms of improved performance at reasonable cost. The second part of the dissertation focuses on the effect of packaging constraints on network performance. Such constraints have important impacts on system architecture, and must be incorporated into network analysis. We focus on architectural clustering as a promising approach to utilize resources efficiently and circumvent implementational difficulties. We find that clustering allows the construction of shared, high bandwidth channels, which are more efficient than dedicated, low bandwidth channels. However, the relative performance of the networks we studied is dependent on system configuration, message granularity and the packaging constraint chosen to be critical. Based on these factors, we can determine the best network for a given system environment.","Made available in DSpace on 2011-05-07T13:08:53Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305558.pdf: 6739938 bytes, checksum: b02b26a20a42b8b40995127efc80d47a (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:50:50Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:23:16-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9305558","(UMI)AAI9305558","http://hdl.handle.net/2142/21446"],"dc:language":["eng"],"dc:rights":["Copyright 1992 Hsu, Tsun-yuk"],"dc:subject":["Computer Science"],"dc:title":["Multiprocessor communications: Design and technology"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:18Z"}