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University of Illinois at Urbana-Champaign
Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits
Abstract
dc:descriptionIt is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Diaz, Carlos Hernando
- Contributors dc:contributor
-
- Kang, Sung Mo
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- Copyright 1993 Diaz, Carlos Hernando
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
-
AAI9329014
(UMI)AAI9329014 - OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/21266