{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21266"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21266","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits","abstract":"It is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).","abstract_html":"It is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).","abstract_has_math":false,"creators":["Diaz, Carlos Hernando"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Kang, Sung Mo"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:03:33Z","date_published":"2011-05-07T13:03:33Z","updated_at":"2026-07-22T22:25:17Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1993 Diaz, Carlos Hernando"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9329014","(UMI)AAI9329014"],"render_values":[{"text":"AAI9329014","href":null,"code":true},{"text":"(UMI)AAI9329014","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21266","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, Sung Mo"]},{"key":"dc:creator","label":"Author","values":["Diaz, Carlos Hernando"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:03:33Z","10000-01-01","1993"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1993 Diaz, Carlos Hernando"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9329014","(UMI)AAI9329014","http://hdl.handle.net/2142/21266"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["It is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).","A new nonlinear mixed 2D-1D thermal simulator, iTSIM, was developed in order to understand and quantify the sensitivity of the power profiles with respect to major thermal parameters of the integrated circuit (IC).","Protection devices with different layout parameters were fabricated and experimentally characterized for EOS. Experimental data indicate that these devices fail with a poly gate filament in the drain edge when subjected to ESD or short-duration EOS events, while extensive device damage is observed for long-duration EOS events revealing onset of thermal runaway. Two-dimensional (2D) device-level electrothermal simulations are used to develop qualitative analysis of both the physical mechanisms leading to device failure and the dependencies of the failure thresholds (power and current profiles) on the layout parameters. Results from this study coupled with heat removal considerations led to a design guideline for source contact placement that is expected to improve the failure thresholds for I/O protection devices of CMOS ICs with grounded substrate.","Thermal instability of an electrically stressed circuit or device is shown to be the result of either thermally induced negative differential resistance (NDR) in resistive regions, or junction second breakdown. Under typical ESD/EOS stress events (transient in nature), the temperature at which thermal instability takes place depends on the level of the stress current. In semiconductor junctions reverse-biased by an EOS event, second breakdown is shown to happen at the time when thermal carrier generation becomes high enough to offset the effects of the mobility degradation and the reduction of the impact ionization rates. Under these circumstances, the time for the onset of second breakdown is shown to depend on the device's geometry and the level of power dissipation.","Circuit level electrothermal models are introduced for resistors, diodes, and bipolar and MOS transistors; they are capable of describing device behaviour up into thermal runaway or second breakdown. (Abstract shortened by UMI.)","Made available in DSpace on 2011-05-07T13:03:33Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9329014.pdf: 5925904 bytes, checksum: bc8a79726cf4b25260634e56acb9a16b (MD5) Previous issue date: 1993","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:49:36Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:22:35-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits"]}]}],"canonical_facts":{"dc:contributor":["Kang, Sung Mo"],"dc:creator":["Diaz, Carlos Hernando"],"dc:date":["2011-05-07T13:03:33Z","10000-01-01","1993"],"dc:description":["It is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).","A new nonlinear mixed 2D-1D thermal simulator, iTSIM, was developed in order to understand and quantify the sensitivity of the power profiles with respect to major thermal parameters of the integrated circuit (IC).","Protection devices with different layout parameters were fabricated and experimentally characterized for EOS. Experimental data indicate that these devices fail with a poly gate filament in the drain edge when subjected to ESD or short-duration EOS events, while extensive device damage is observed for long-duration EOS events revealing onset of thermal runaway. Two-dimensional (2D) device-level electrothermal simulations are used to develop qualitative analysis of both the physical mechanisms leading to device failure and the dependencies of the failure thresholds (power and current profiles) on the layout parameters. Results from this study coupled with heat removal considerations led to a design guideline for source contact placement that is expected to improve the failure thresholds for I/O protection devices of CMOS ICs with grounded substrate.","Thermal instability of an electrically stressed circuit or device is shown to be the result of either thermally induced negative differential resistance (NDR) in resistive regions, or junction second breakdown. Under typical ESD/EOS stress events (transient in nature), the temperature at which thermal instability takes place depends on the level of the stress current. In semiconductor junctions reverse-biased by an EOS event, second breakdown is shown to happen at the time when thermal carrier generation becomes high enough to offset the effects of the mobility degradation and the reduction of the impact ionization rates. Under these circumstances, the time for the onset of second breakdown is shown to depend on the device's geometry and the level of power dissipation.","Circuit level electrothermal models are introduced for resistors, diodes, and bipolar and MOS transistors; they are capable of describing device behaviour up into thermal runaway or second breakdown. (Abstract shortened by UMI.)","Made available in DSpace on 2011-05-07T13:03:33Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9329014.pdf: 5925904 bytes, checksum: bc8a79726cf4b25260634e56acb9a16b (MD5) Previous issue date: 1993","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:49:36Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:22:35-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9329014","(UMI)AAI9329014","http://hdl.handle.net/2142/21266"],"dc:language":["eng"],"dc:rights":["Copyright 1993 Diaz, Carlos Hernando"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:17Z"}