Automatic test generation for bit-serial VLSI digital signal processors

Linear digital signal processors, commonly implemented using silicon compilers in bit-serial architecture, are very difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical testing approach has been proposed, integrating three automatic test generators. FEAST (Functional Extractor and Sequential Test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. SEAT (Sequential Array Test generator) and CREST (Constrained Sequential Test generator) operate at the low level description of the individual modules.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Roy, Rabindra Kumar

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1992 Roy, Rabindra Kumar

Language dc:language

eng

Identifier

AAI9236586
(UMI)AAI9236586

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20975