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Showing 1 to 13 of 13 for “"Bit-Serial"”.
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Programming Languages for Bit-Serial Array Machines
Many high-level languages have been created or are under development for large nearest-neighbor connected multiprocessors, such as the ILLIAC IV, the ICL DAP, and the Goddard-Goodyear MPP. These higher-level languages are intended to make these machines easier to program.
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Automatic test generation for bit-serial VLSI digital signal processors
… commonly implemented using silicon compilers in bit-serial architecture, are very difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical testing approach has been proposed, integrating three automatic …
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An Array Simulator Generator
… system which facilitates the production of bit-serial array computer simulators. The resultant programs emulate the action of a target machine to the resolution of single instructions. The timing of interactions between independent modules is faithfully reproduced. The system is useful for …
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Serialization and asynchronous techniques for reliable network-on-chip communication
… thesis investigates the use of compression in bit-serial point-to-point links as a means of increasing the available bandwidth of the links in NoC. A bit-serial link reduces the cost of interconnect by reducing the number of wires, but at the expense of reduced throughput. Compression is used …
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Secure Circuits: Efficient hardware countermeasures against physical side-channel attacks
… the problem. Firstly, we introduce MBSNTT (Multi-Bit Serial Number Theoretic Transform Accelerator) to accelerate the NTT operation in Homomorphic Encryption. In this implementation, we apply processing-in-memory techniques to the NTT operation, thereby achieving high parallelism. In the second …
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A comparative study of synchronous and self-timed systolic array architectures.
… that operate correctly in the presence of arbitrary delays at all levels in their design. As a consequence, RTZ and NRTZ versions of an existing systolic array architecture, namely the Single instruction Systolic Array (SISA), have been developed in order to investigate the potential for …
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The testability of regular logic structures
… of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.
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Compiling and optimizing spreadsheets for FPGA and multicore execution
… through a circuit. Parallelization of a 64-bit serial leading-zero-counter is demonstrated with Catalyst. Fault tolerance macros were also developed in Catalyst to protect against dynamic faults and to offset costs associated with testing semiconductors for static defects. A model for …
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Area-constrained frequency estimation for focal plane arrays
… is combined with the area estimates of a 1-bit full adder (FA) and a 1-bit register in a 65 nm CMOS process to obtain the area costs of the D-DHT and the DFT. Results show that the D-DHT achieves ~2x area reduction over the DFT with no significant impact on detection accuracy. However, …
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Signal estimation techniques using Lp-norm optimal stack filters with applications to image and video processing
… complexities of the conventional parallel and bit-serial algorithms for stack filtering depend on the number of grey levels of an input image (signal). In this thesis, two new hardware-oriented algorithms for multidimensional stack filtering, for which the time-area complexity depends on the …
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Design and Analysis of Four Architectures for FPGA-Based Cellular Computing
… be impractical for some researchers due to prohibitive costs and limited availability. These researchers might be better served by a more personal solution such as a "hardware acceleration" peripheral for a PC. FPGAs are the ideal device for the task: their configurability allows a problem to be …
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Application Specific Domain Co-design Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things
L'abstract è presente nell'allegato / the abstract is in the attachment