Adaptive and integrated data cache prefetching for shared memory multiprocessors

Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Gornish, Edward H.

• Computer Science

Statement dc:rights

• Copyright 1995 Gornish, Edward H.

Language dc:language

eng

Identifier

(UMI)AAI9522113
AAI9522113

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20929