{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/20929"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/20929","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Adaptive and integrated data cache prefetching for shared memory multiprocessors","abstract":"Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.","abstract_html":"Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.","abstract_has_math":false,"creators":["Gornish, Edward H."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T12:53:24Z","date_published":"2011-05-07T12:53:24Z","updated_at":"2026-07-22T22:25:16Z","subjects":["Computer Science"],"languages":["eng"],"rights":["Copyright 1995 Gornish, Edward H."],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9522113","AAI9522113"],"render_values":[{"text":"(UMI)AAI9522113","href":null,"code":true},{"text":"AAI9522113","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/20929","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Gornish, Edward H."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T12:53:24Z","10000-01-01","1995"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1995 Gornish, Edward H."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9522113","http://hdl.handle.net/2142/20929","AAI9522113"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.","In this dissertation, we present novel data prefetching techniques, and we evaluate the performance of data prefetching in a multiprocessor environment, via a detailed simulation of the memory subsystem. We first present an adaptive hardware prefetching technique that uses runtime information to decide when to generate prefetches. We show that the ideal time to issue prefetches depends on system characteristics such as available bandwidth. We next propose an integrated prefetching approach. This scheme attempts to use the best aspects of both hardware and software prefetching, so as to yield a better overall scheme. We give a detailed description of the compiler analysis necessary for integrated prefetching. The performance of integrated prefetching is compared to software and hardware prefetching, and we show the effect of adapting the scheduling of prefetches at compile time. Finally, we discuss approaches that combine integrated prefetching with the adaptive hardware prefetching technique.","Made available in DSpace on 2011-05-07T12:53:24Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9522113.pdf: 5536576 bytes, checksum: bc1cf6968b38f0b9be81c2cc5cd908d1 (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:47:19Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:21:21-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Adaptive and integrated data cache prefetching for shared memory multiprocessors"]}]}],"canonical_facts":{"dc:creator":["Gornish, Edward H."],"dc:date":["2011-05-07T12:53:24Z","10000-01-01","1995"],"dc:description":["Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different approaches. Prefetch adaptivity, which involves adapting when prefetches are issued for different data, is another important issue.","In this dissertation, we present novel data prefetching techniques, and we evaluate the performance of data prefetching in a multiprocessor environment, via a detailed simulation of the memory subsystem. We first present an adaptive hardware prefetching technique that uses runtime information to decide when to generate prefetches. We show that the ideal time to issue prefetches depends on system characteristics such as available bandwidth. We next propose an integrated prefetching approach. This scheme attempts to use the best aspects of both hardware and software prefetching, so as to yield a better overall scheme. We give a detailed description of the compiler analysis necessary for integrated prefetching. The performance of integrated prefetching is compared to software and hardware prefetching, and we show the effect of adapting the scheduling of prefetches at compile time. Finally, we discuss approaches that combine integrated prefetching with the adaptive hardware prefetching technique.","Made available in DSpace on 2011-05-07T12:53:24Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9522113.pdf: 5536576 bytes, checksum: bc1cf6968b38f0b9be81c2cc5cd908d1 (MD5) Previous issue date: 1995","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:47:19Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:21:21-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["(UMI)AAI9522113","http://hdl.handle.net/2142/20929","AAI9522113"],"dc:language":["eng"],"dc:rights":["Copyright 1995 Gornish, Edward H."],"dc:subject":["Computer Science"],"dc:title":["Adaptive and integrated data cache prefetching for shared memory multiprocessors"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:16Z"}