Data preload for superscalar and VLIW processors

Processor design techniques, such as pipelining, superscalar, and VLIW, have dramatically decreased the average number of clock cycles per instruction. As a result, each execution cycle has become more significant to overall system performance. To maximize the effectiveness of each cycle, one must expose instruction-level parallelism and employ memory latency tolerant techniques. However, without special architecture support, a superscalar compiler cannot effectively accomplish these two tasks in the presence of control and memory access dependences.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Chen, William Yu-Wei, Jr.

Contributors dc:contributor

• Hwu, Wen-Mei W.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1993 Chen, William Yu-Wei, Jr

Language dc:language

eng

Identifier

AAI9411585
(UMI)AAI9411585

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20761