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Showing 1 to 20 of 31 for “"Processor Design"”.

  1. Verification-Aware Processor Design

    … critical as well. Currently, ensuring that processor designs are correct represents a major challenge for the computing industry consuming the majority (up to 70%) of the resources allocated for the creation of a new processor. Looking towards the future, we see that with each new processor

    duke Repository record for Verification-Aware Processor Design (opens in a new tab)

  2. Low-voltage embedded biomedical processor design

    … with body-worn or implanted sensors. Digital processors on such sensors serve to analyze signals in real-time and extract key features for transmission or storage. To support diverse and evolving applications, the processor should be flexible, and to extend sensor operating lifetime, the …

    mit Repository record for Low-voltage embedded biomedical processor design (opens in a new tab)

  3. Analysis of Hardware Sorting Units in Processor Design

    … accelerate sorting include the use of multiple processors or moving the sorting operation to a GPU. The use of multiple processors or a GPU can lead to increased energy consumption and heat produced by the device as compared to a single-core GPU-less implementation. To address these problems, …

    calpoly Repository record for Analysis of Hardware Sorting Units in Processor Design (opens in a new tab)

  4. Self-tuning dynamic voltage scaling techniques for processor design

    … performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature …

    texas Repository record for Self-tuning dynamic voltage scaling techniques for processor design (opens in a new tab)

  5. Labyrinth Seal Preprocessor and Post-Processor Design and Parametric Study

    … for a labyrinth seal analysis program, has been designed herein. In order to accurately predict the excitation force, proper modeling of labyrinth leak path is important. Thus, the front-end developed herein incorporates a leak-path geometric diagram for visual analysis of labyrinth leak path and …

    vt Repository record for Labyrinth Seal Preprocessor and Post-Processor Design and Parametric Study (opens in a new tab)

  6. A co-processor design to support MPI primitives in configurable multiprocessor designs

    … (MIPI) is a widely used standard for inter-processor communication in parallel computers. This standard is normally implemented in software, thus resulting in large communication latencies. A hardware implementation can reduce communication latencies significantly, thereby increasing the …

    njit Repository record for A co-processor design to support MPI primitives in configurable multiprocessor designs (opens in a new tab)

  7. Data preload for superscalar and VLIW processors

    Processor design techniques, such as pipelining, superscalar, and VLIW, have dramatically decreased the average number of clock cycles per instruction. As a result, each execution cycle has become more significant to overall system performance. To maximize the effectiveness of each cycle, one must …

    uiuc Repository record for Data preload for superscalar and VLIW processors (opens in a new tab)

  8. Asynchronous MIPS Processors: Educational Simulations

    … has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have …

    calpoly Repository record for Asynchronous MIPS Processors: Educational Simulations (opens in a new tab)

  9. AXCIS : rapid processor architectural exploration using canonical instruction segments

    In the early stages of processor design, computer architects rely heavily on simulation to explore a very large design space. Although detailed microarchitectural simulation is effective and widely used for evaluating different processor configurations, long simulation times and a limited …

    mit Repository record for AXCIS : rapid processor architectural exploration using canonical instruction segments (opens in a new tab)

  10. Pensieve: Microarchitectural Modeling for Security Evaluation

    … estimation of performance, area, and energy of a processor design. With the advent of speculative execution attacks and their security concerns, these traditional modeling techniques fall short when used for security evaluation of defenses against these attacks. This thesis presents Pensieve, a …

    mit Repository record for Pensieve: Microarchitectural Modeling for Security Evaluation (opens in a new tab)

  11. Flexible MIPS soft processor architecture

    The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to …

    mit Repository record for Flexible MIPS soft processor architecture (opens in a new tab)

  12. Use of high-level design information for enabling automation of fine-grained power gating

    … through power gating requires considerable design and verification effort. Conventionally, extensive analysis is required for dividing a heterogeneous design into power domains and generating control signals for power switches because of the need to preserve design behavior. In this thesis, …

    mit Repository record for Use of high-level design information for enabling automation of fine-grained power gating (opens in a new tab)

  13. Multi-Domain Coincidence Processing and Memory Architecture for Real-Time Geiger Mode LiDAR

    … space. This paper proposes a multi-processor system architecture and memory management techniques for performing orientation-compensated histogram generation and peak detection to filter the LiDAR data stream, removing redundancy and spurious outputs. The multi-processor design, …

    mit Repository record for Multi-Domain Coincidence Processing and Memory Architecture for Real-Time Geiger Mode LiDAR (opens in a new tab)

  14. Designing a Compiler for a Distributed Memory Parallel Computing System

    The SCMP processor presents a unique approach to processor design: integrating multiple processors, a network, and memory onto a single chip. The benefits to this design include a reduction in overhead incurred by synchronization, communication, and memory accesses. To properly determine its …

    vt Repository record for Designing a Compiler for a Distributed Memory Parallel Computing System (opens in a new tab)

  15. FPGA-based implementation of parallel graph partitioning

    … methods to data processing and VLSI circuit design. Many algorithms have been developed to solve this problem. Of special interest is multilevel graph partitioning that provides a very efficient solution. This method can also be parallelized and implemented on various multiprocessor …

    njit Repository record for FPGA-based implementation of parallel graph partitioning (opens in a new tab)

  16. Architectural Support for Protecting Memory Integrity and Confidentiality

    This dissertation describes efficient design of tamper-resistant secure processor and cryptographic memory protection model that will strength security of a computing system. The thesis proposes certain cryptographic and security features integrated into the general purpose processor and computing …

    gatech Repository record for Architectural Support for Protecting Memory Integrity and Confidentiality (opens in a new tab)

  17. Coverage analysis for assertions and emulation based verification

    … critical in pre-silicon verification of hardware designs for assessing the completeness of verification and identifying inadequately exercised areas of the design. It is widely integrated in the simulation based verification flow in the hardware industry. In this thesis, we provide solutions to …

    uiuc Repository record for Coverage analysis for assertions and emulation based verification (opens in a new tab)

  18. Efficient mobile computing

    … From a computer architect point of view, processor design for such computer systems is a complex problem. Since the Li-ion battery manufacturing technology is strictly limited by physical and technological limitations, the new generation of mobile processors should have a better energy …

    uiuc Repository record for Efficient mobile computing (opens in a new tab)

  19. Side-Channel Attacks in RISC-V BOOM Front-end

    … a significant threat to the security of modern processors. The RISC-V BOOM core is an open-source modern processor design widely utilized in research and industry. It enables experimentation with microarchitec- tures and memory hierarchies for optimized performance in various workloads. The …

    vt Repository record for Side-Channel Attacks in RISC-V BOOM Front-end (opens in a new tab)

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