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Massachusetts Institute of Technology

AXCIS : rapid processor architectural exploration using canonical instruction segments

Abstract

dc:description.abstract

In the early stages of processor design, computer architects rely heavily on simulation to explore a very large design space. Although detailed microarchitectural simulation is effective and widely used for evaluating different processor configurations, long simulation times and a limited time-to-market severely constrain the number of design points explored. This thesis presents AXCIS, a framework for fast and accurate early-stage design space exploration. Using instruction segments, a new primitive for extracting and representing simulation-critical data from full dynamic traces, AXCIS compresses the full dynamic trace into a table of canonical instruction segments (CIST). CISTs are not only small, but also very representative of the dynamic trace. Therefore, given a CIST and a processor configuration, AXCIS can quickly and accurately estimate performance metrics such as instructions per cycle (IPC). This thesis applies AXCIS to in-order superscalar processors, which are becoming more popular with the emergence of chip multiprocessors (CMP). For 24 SPEC CPU2000 benchmarks and all simulated configurations, AXCIS achieves an average IPC error of 2.6% and is over four orders of magnitude faster than conventional detailed simulation.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2005

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Liu, Rose F. (Rose Frances)
Advisor dc:contributor.advisor
  • Krste Asanović.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/36792
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/36792

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Liu, Rose F. (Rose Frances). AXCIS : rapid processor architectural exploration using canonical instruction segments. Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/36792