Data prefetch mechanisms for accelerating symbolic and numeric computation

Despite rapid increases in CPU performance, the primary obstacles to achieving higher performance in contemporary processor organizations remain control and data hazards. Primary data cache misses are responsible for the majority of the data hazards. With CPU primary cache sizes limited by clock cycle time constraints, the performance of future CPUs is effectively going to be limited by the number of primary data cache misses whose penalty cannot be masked.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Mehrotra, Sharad

Contributors dc:contributor

• Padua, David A.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1996 Mehrotra, Sharad

Language dc:language

eng

Identifier

9780591089059
AAI9702609
(UMI)AAI9702609

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20344