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Showing 1 to 14 of 14 for “"Data cache"”.
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Split array and scalar data cache: A comprehensive study of data cache organization.
Existing cache organization suffers from the inability to distinguish different types of localities, and non-selectively cache all data rather than making any attempt to take special advantage of the locality type. This causes unnecessary movement of data among the levels of the memory hierarchy …
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Adaptive and integrated data cache prefetching for shared memory multiprocessors
… processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data prefetching can be controlled by hardware, software or a combination of the two, and there are many tradeoffs associated with these different …
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Data prefetch mechanisms for accelerating symbolic and numeric computation
… processor organizations remain control and data hazards. Primary data cache misses are responsible for the majority of the data hazards. With CPU primary cache sizes limited by clock cycle time constraints, the performance of future CPUs is effectively going to be limited by the number of …
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Scalable primary cache memory architectures
… of this trend has included the growth of on-chip caches which in modern processor can be as large as 2MB. However, as smaller technologies become prevalent, achieving low average memory access time by simply scaling existing designs becomes more difficult because of process limitations. This …
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Store Buffers : implementing single cycle store instructions in write-through, write-back and set associative caches
… cases the tag check must be performed before the data can be written into the data cache. Store buffers allow a store instruction to read the cache tag as it. passes through the pipe while keeping the store instruction data buffered in a backup register until the data cache is free. This strategy …
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Cache optimizations for stream programs
… on a set of transformations that either reduce cache-miss rate or reduce the number of memory accesses for the class of streaming applications, which are becoming increasingly prevalent in embedded, desktop and high-performance processing. A fully automated optimization algorithm is presented …
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Exploiting multiprocessor memory hierarchies for operating systems
… systems. The operating system instruction cache misses are reduced by 81% using a code reorganization scheme tailored to the operating system, guarded sequential prefetching, and stream buffers. The operating system data cache misses are reduced by 53% using a DMA-like pipelined block …
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Improving performance and security of indirect memory references on speculative execution machines
… Traditional hardware techniques such as caches and speculative execution are ineffective on demanding workloads, such as in-memory databases, machine learning, and graph analytics. While terabytes of DRAM are now available in public cloud machines, indirect memory references in large …
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Soft-error resilient on-chip memory structures
… strikes in on-chip memory structures, such as L1 data/instruction caches and register files, have become an increasing challenge in designing new generation reliable microprocessors. Due to their transient/random nature, soft errors cannot be captured by traditional verification and testing …
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Energy-efficient mechanisms for managing on-chip storage in throughput processors
… We study both a hardware-managed register file cache and a software-managed operand register file. We evaluate the energy tradeoffs in varying the number of levels and the capacity of each level in the hierarchy. Our most efficient design reduces register file energy by 54%. Beyond the register …
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Performance Modeling and Prediction for the Scalable Solution of Partial Differential Equations on Unstructured Grids
… available memory bandwidth, low ratio of work to data size (good algorithmic efficiency), and nonscaling cost of synchronization and gather/scatter operations (for a fixed problem size scaling). This dissertation also illustrates how to reuse the legacy scientific and engineering software within a …
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Energy-aware system design using circuit reconfigurability with a focus on low-power SRAMs
… reconfigurability. In this regard, the data cache is designed to be reconfigurable in terms of set associativity (1-4 sets) and size (1kB to 4kB per set). Furthermore, the system is designed to enable voltage and frequency scaling. Energy monitoring circuits that are capable of …
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Fast and Scalable Architectures and Algorithms for the Computation of the Forward and Inverse Discrete Periodic Radon Transform with Applications to 2D Convolutions and Cross-Correlations
… memory components when selecting the input data for the adder trees, and (iii) an image block-based approach to DPRT computation that can fit the proposed architecture to available resources, and as a result, for an NxN image (N prime), the proposed approach can compute up to N^2 additions …
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Comprehensive variation-aware aging simulator for logic timing and SRAM stability
This research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of …