Task flow: A novel approach to fine-grain wafer-scale parallel computing

This thesis introduces a parallel computer architecture known as task flow. Simple replicated cells contain both memory packets and processing logic. Each memory packet contains a data field, the next instruction, and a link. Transmission packets flow between memory packets to communicate instructions and temporary data values. Program execution is performed by multiple tasks that communicate through memory variables. Each task may remain local to one cell for extended periods or may flow between cells with as few as one instruction executed in each cell.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Horst, Robert Whiting

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1991 Horst, Robert Whiting

Language dc:language

eng

Identifier

AAI9136618
(UMI)AAI9136618

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20291