Performance-driven chip floorplanning and global routing

In this thesis algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Date dc:date

10000-01-01

Author dc:creator

• Prasitjutrakul, Somchai

Contributors dc:contributor

• Kubitz, William J.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1991 Prasitjutrakul, Somchai

Language dc:language

eng

Identifier

AAI9136703
(UMI)AAI9136703

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19413