{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/19413"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/19413","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Performance-driven chip floorplanning and global routing","abstract":"In this thesis algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.","abstract_html":"In this thesis algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.","abstract_has_math":false,"creators":["Prasitjutrakul, Somchai"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Kubitz, William J."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"10000-01-01","date_published":"10000-01-01","updated_at":"2026-07-22T22:25:12Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1991 Prasitjutrakul, Somchai"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9136703","(UMI)AAI9136703"],"render_values":[{"text":"AAI9136703","href":null,"code":true},{"text":"(UMI)AAI9136703","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/19413","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kubitz, William J."]},{"key":"dc:creator","label":"Author","values":["Prasitjutrakul, Somchai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["10000-01-01","1991","2011-05-07T12:06:46Z"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1991 Prasitjutrakul, Somchai"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9136703","(UMI)AAI9136703","http://hdl.handle.net/2142/19413"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this thesis algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.","Made available in DSpace on 2011-05-07T12:06:46Z (GMT). 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Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.","Made available in DSpace on 2011-05-07T12:06:46Z (GMT). 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