Simulation of faults causing analog behavior in digital circuits

The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Yang, Fred Lei

Contributors dc:contributor

• Saleh, Resve A.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1992 Yang, Fred Lei

Language dc:language

eng

Identifier

AAI9305740
(UMI)AAI9305740

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19306