{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/19306"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/19306","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Simulation of faults causing analog behavior in digital circuits","abstract":"The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches.","abstract_html":"The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches.","abstract_has_math":false,"creators":["Yang, Fred Lei"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Saleh, Resve A."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T12:03:22Z","date_published":"2011-05-07T12:03:22Z","updated_at":"2026-07-22T22:25:12Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1992 Yang, Fred Lei"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305740","(UMI)AAI9305740"],"render_values":[{"text":"AAI9305740","href":null,"code":true},{"text":"(UMI)AAI9305740","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/19306","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Saleh, Resve A."]},{"key":"dc:creator","label":"Author","values":["Yang, Fred Lei"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T12:03:22Z","10000-01-01","1992"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1992 Yang, Fred Lei"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305740","(UMI)AAI9305740","http://hdl.handle.net/2142/19306"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches.","Made available in DSpace on 2011-05-07T12:03:22Z (GMT). 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In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. 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