Distributed scalable model for CMOS FET power amplifier

Integrated circuits are very popular for understandable reasons. A circuit implemented within an IC is more cost effective and reliable. A vast majority of ICs are created using silicon because it is cheap and the technology is mature. Unfortunately, communications power amplifiers have been scarce, due to the electrical advantages provided by III-V semiconductors. In order to reach similar power levels, power amplifiers implemented on silicon require larger transistors. It is common practice to create such transistors using multiple smaller transistors connected in parallel. As the frequency of operation increases, the connections between the smaller transistors affect the overall system’s behavior. Current industry standard models do not accurately compensate for these connections. This work discusses the development and results for a high-multiplicity MOS FET power amplifier model using layout transmission line considerations. ii

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Graham, Sean R.

Contributors dc:contributor

• Feng, Milton

• Radio Frequency (RF)+
• Complementary metal–oxide–semiconductor (CMOS)
• Power Amplifier

Statement dc:rights

• COpyright 2010 Sean R. Graham

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/18454

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/18454