Characterization and Engineering of Error Statistics for Reliable Computation

We make a case for developing statistical error models of nanoscale circuits, employing these for designing robust systems, and engineering error-statistics to enhance the performance of various robust design techniques. A simple additive error model is presented for arithmetic computations. The proposed error model is shown to be a strong function of the architecture, and a weak function of the input statistics, thus enabling a one-time off-line characterization similar to delay and power characterization done presently. In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Lee, Yu-Hung

Contributors dc:contributor

• Shanbhag, Naresh R.

• robust system design
• error statistics
• diversity technique
• error model

Statement dc:rights

• Copyright 2010 Yu-Hung Lee

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/18281

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/18281