{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18281"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18281","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Characterization and Engineering of Error Statistics for Reliable Computation","abstract":"We make a case for developing statistical error models of nanoscale circuits, employing these for designing robust systems, and engineering error-statistics to enhance the performance of various robust design techniques. A simple additive error model is presented for arithmetic computations. The proposed error model is shown to be a strong function of the architecture, and a weak function of the input statistics, thus enabling a one-time off-line characterization similar to delay and power characterization done presently. In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.","abstract_html":"We make a case for developing statistical error models of nanoscale circuits, employing these for designing robust systems, and engineering error-statistics to enhance the performance of various robust design techniques. A simple additive error model is presented for arithmetic computations. The proposed error model is shown to be a strong function of the architecture, and a weak function of the input statistics, thus enabling a one-time off-line characterization similar to delay and power characterization done presently. In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.","abstract_has_math":false,"creators":["Lee, Yu-Hung"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-14T22:44:30Z","date_published":"2011-01-14T22:44:30Z","updated_at":"2026-07-22T22:25:11Z","subjects":["robust system design","error statistics","diversity technique","error model"],"languages":["en"],"rights":["Copyright 2010 Yu-Hung Lee"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/18281","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Lee, Yu-Hung"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-01-14T22:44:30Z","2010-12"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["robust system design","error statistics","diversity technique","error model"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2010 Yu-Hung Lee"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/18281"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["We make a case for developing statistical error models of nanoscale circuits, employing these for designing robust systems, and engineering error-statistics to enhance the performance of various robust design techniques. A simple additive error model is presented for arithmetic computations. The proposed error model is shown to be a strong function of the architecture, and a weak function of the input statistics, thus enabling a one-time off-line characterization similar to delay and power characterization done presently. In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-12-09T18:14:26Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Lee_Yu-Hung.pdf: 7820755 bytes, checksum: 51b21feac3093910aa61900db7c545d7 (MD5)","Made available in DSpace on 2011-01-14T22:44:30Z (GMT). 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In addition, we propose architectural diversity and scheduling diversity to engineer the occurrence of independent errors as required by robust system design techniques such as soft N-modular redundancy (NMR). Finally, we employ error statistics to develop soft dual-MR (DMR) and triple-MR (TMR) techniques for the adder operation and the filter design. All quantitative results are demonstrated in a commercial 45 nm CMOS process.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-12-09T18:14:26Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Lee_Yu-Hung.pdf: 7820755 bytes, checksum: 51b21feac3093910aa61900db7c545d7 (MD5)","Made available in DSpace on 2011-01-14T22:44:30Z (GMT). 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