High-Speed Serial Data Link Design and Simulation

This thesis describes the modeling and simulation of 10 Gb/s serial data link architectures. The first architecture uses a continuous-time receiver equalizer to equalize a channel with known frequency response. The second incorporates an adaptive decision feedback equalizer (DFE) for use in unknown or time-varying channels.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2010

Author dc:creator

• Lee, Edward W.

Contributors dc:contributor

• Schutt-Ainé, José E.

• Serial Link Receiver
• Data Recovery
• Adaptive Equalization
• Decision Feedback Equalizer
• Decision Feedback Equalizer (DFE) Receiver

Statement dc:rights

• Copyright 2009 Edward W. Lee

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/14727

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/14727