A high resolution programmable thermal test chip

As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois Urbana-Champaign

Year dc:date

2025

Author dc:creator

• Wu, Zaizhou

Contributors dc:contributor

• Kumar, Rakesh

• thermal test chip

Statement dc:rights

• Copyright 2025 Zaizhou Wu

Language dc:language

en

Handle dc:identifier

https://hdl.handle.net/2142/132815

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/132815