{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/132815"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/132815","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A high resolution programmable thermal test chip","abstract":"As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.","abstract_html":"As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.","abstract_has_math":false,"creators":["Wu, Zaizhou"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kumar, Rakesh"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-12","date_published":"2025-12","updated_at":"2026-07-22T22:25:07Z","subjects":["thermal test chip"],"languages":["en"],"rights":["Copyright 2025 Zaizhou Wu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/132815","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kumar, Rakesh"]},{"key":"dc:creator","label":"Author","values":["Wu, Zaizhou"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-12","2025-12-11"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["thermal test chip"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Zaizhou Wu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/132815"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Zaizhou Wu, accepted the attached license on 2025-12-11 at 12:01.","The student, Zaizhou Wu, submitted this Thesis for approval on 2025-12-11 at 12:06.","This Thesis was approved for publication on 2025-12-11 at 13:10.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23135 on 2026-02-19 at 20:10:12"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A high resolution programmable thermal test chip"]}]}],"canonical_facts":{"dc:contributor":["Kumar, Rakesh"],"dc:creator":["Wu, Zaizhou"],"dc:date":["2025-12","2025-12-11"],"dc:description":["As silicon technology continues to scale, power densities in integrated circuits are rising, driving the need for more accurate and fine-grained thermal characterization methods. While numerical simulation remains a powerful tool for predicting on-chip temperature distributions, its accuracy ultimately depends on model assumptions and boundary conditions. To bridge this gap, A design and implementation of a dedicated thermal test chip that enables direct, high-resolution experimental platform is presented. The chip, taped out on TSMC 65 nm process, integrates a 12×14 array of controllable heaters using real datapath elements and distributed temperature sensors, allowing systematic evaluation of transient and steady-state thermal responses of behavior equivariant to real chips.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Zaizhou Wu, accepted the attached license on 2025-12-11 at 12:01.","The student, Zaizhou Wu, submitted this Thesis for approval on 2025-12-11 at 12:06.","This Thesis was approved for publication on 2025-12-11 at 13:10.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23135 on 2026-02-19 at 20:10:12"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/132815"],"dc:language":["en"],"dc:rights":["Copyright 2025 Zaizhou Wu"],"dc:subject":["thermal test chip"],"dc:title":["A high resolution programmable thermal test chip"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:07Z"}